Presentation
SLC-Based Real-Time Traffic Buffering with DRAM Row-Aware Write Back
DescriptionReal-time (RT) traffic in modern SoCs is often assigned the highest priority to meet strict latency requirements during traffic bursts. However, aggressively servicing urgent RT requests forces immediate DRAM access, breaking row locality and increasing read/write direction switching. This degrades DRAM efficiency and causes non-real-time (NRT) traffic to be repeatedly delayed under shared resource contention, reducing overall system performance.
We propose an SLC-based Real-Time write buffering mechanism that decouples RT urgency from DRAM scheduling. RT write requests are absorbed by SLC(System-level-cache) and acknowledged immediately preserving bounded RT latency while allowing RT traffic priority to be safely lowered.
When draining RT data buffered in the SLC to DRAM, deferred writebacks are issued only when the DRAM path is less congested. To further improve memory efficiency, the SLC groups writebacks targeting the same DRAM row and issue them consecutively. A small DRAM Row-Aware Buffer (DRAB) tracks unique row addresses of buffered RT writes and enables row-grouped writeback generation.
This approach reduces priority-driven interference, improves DRAM scheduling efficiency, and allows NRT traffic to make steady forward progress with minimal architectural changes.
We propose an SLC-based Real-Time write buffering mechanism that decouples RT urgency from DRAM scheduling. RT write requests are absorbed by SLC(System-level-cache) and acknowledged immediately preserving bounded RT latency while allowing RT traffic priority to be safely lowered.
When draining RT data buffered in the SLC to DRAM, deferred writebacks are issued only when the DRAM path is less congested. To further improve memory efficiency, the SLC groups writebacks targeting the same DRAM row and issue them consecutively. A small DRAM Row-Aware Buffer (DRAB) tracks unique row addresses of buffered RT writes and enables row-grouped writeback generation.
This approach reduces priority-driven interference, improves DRAM scheduling efficiency, and allows NRT traffic to make steady forward progress with minimal architectural changes.
Event Type
Engineering Poster
TimeWednesday, July 293:00pm - 4:00pm PDT
LocationDAC Pavilion, Exhibit Floor
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