Presentation
Google's Faster and Earlier Chip Finishing with Seamless Power Grid Enhancement Integration
DescriptionAt advanced nodes beyond 3nm, IR-drop challenges intensify, demanding solutions that combine signoff-quality results with design cycle efficiency. We present an evolved power grid enhancement methodology that seamlessly integrates with leading place-and-route tools, enabling automated invocation during iterative design stages. Our approach uniquely combines OASIS and LEF/DEF formats: leveraging OASIS for maximum via and stripe insertion with signoff-quality DRC compliance, while LEF/DEF enables operation on designs with power grid shorts common in pre-closure iterations.
The methodology incorporates multi-dimensional timing-aware optimization, including net-type-based spacing, automatic track skipping around clock nets, highly timing-critical net avoidance, and delta spacing across metal layers. These protections enable aggressive power grid enhancement with minimal timing impact. Additionally, enhanced via stapling reinforces vertical connectivity in congested layers using an optimized algorithm that maximizes insertion rate while maintaining fast turnaround time. Applied to multiple designs, via stapling achieves 36.6% insertion improvement over P&R tools with up to 13.68× faster runtime, while power grid stripe insertion achieves 10% average IR-drop reduction (up to 17.3%) with only 2% TNS impact. Both maintain signoff-clean DRC results.
This evolution from our DAC 2024 work delivers signoff-quality fixes earlier in the design cycle with short resilience, streamlining designer experience and accelerating closure.
The methodology incorporates multi-dimensional timing-aware optimization, including net-type-based spacing, automatic track skipping around clock nets, highly timing-critical net avoidance, and delta spacing across metal layers. These protections enable aggressive power grid enhancement with minimal timing impact. Additionally, enhanced via stapling reinforces vertical connectivity in congested layers using an optimized algorithm that maximizes insertion rate while maintaining fast turnaround time. Applied to multiple designs, via stapling achieves 36.6% insertion improvement over P&R tools with up to 13.68× faster runtime, while power grid stripe insertion achieves 10% average IR-drop reduction (up to 17.3%) with only 2% TNS impact. Both maintain signoff-clean DRC results.
This evolution from our DAC 2024 work delivers signoff-quality fixes earlier in the design cycle with short resilience, streamlining designer experience and accelerating closure.
Event Type
Engineering Poster
Engineering Presentation
TimeWednesday, July 293:00pm - 3:45pm PDT
LocationDAC Pavilion, Exhibit Floor