Presentation
Comprehensive SoC Power System Verification Using Optimized Mixed-Signal Verification Methodology
DescriptionPower systems are a critical component of the modern system on chips (SoCs) and present formidable mixed-signal verification challenges due to increasing design complexity and diverse power requirements. Designers face hurdles like managing numerous power domains, operating modes, intricate power sequencing, state transitions, and critical analog-digital interactions at domain boundaries. Furthermore, verifying complex Unified Power Format (UPF) strategies for isolation and retention adds significant complexity. Traditional full SPICE simulations for comprehensive power state validation are prohibitively time-consuming, often requiring weeks of runtime and delaying time-to-market by months.
To address these profound limitations, Microchip, in collaboration with Siemens EDA, developed an optimized mixed-signal verification methodology for comprehensive SoC power system validation. This innovative approach, leveraging Siemens EDA's AI accelerated Solido Simulation Suite employs a digital-on-top strategy, seamlessly integrating high-fidelity SPICE views for critical analog modules with high-performance digital simulation for the broader RTL design and UPF strategies.
In this presentation, we will detail this novel methodology and demonstrate how it achieves more than 22X runtime reduction for power states simulation without compromising accuracy, thereby enabling rapid and accurate verification of critical power management scenarios. This approach leads to improving verification coverage, Silicon quality and accelerating time-to-market for robust, energy-efficient SoCs.
To address these profound limitations, Microchip, in collaboration with Siemens EDA, developed an optimized mixed-signal verification methodology for comprehensive SoC power system validation. This innovative approach, leveraging Siemens EDA's AI accelerated Solido Simulation Suite employs a digital-on-top strategy, seamlessly integrating high-fidelity SPICE views for critical analog modules with high-performance digital simulation for the broader RTL design and UPF strategies.
In this presentation, we will detail this novel methodology and demonstrate how it achieves more than 22X runtime reduction for power states simulation without compromising accuracy, thereby enabling rapid and accurate verification of critical power management scenarios. This approach leads to improving verification coverage, Silicon quality and accelerating time-to-market for robust, energy-efficient SoCs.
Event Type
Engineering Poster
Engineering Presentation
TimeWednesday, July 293:00pm - 3:45pm PDT
LocationDAC Pavilion, Exhibit Floor
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