Presentation
Bridging Analog Fidelity and Digital Performance in Chiplet Interface Mixed-Signal IP Verification
DescriptionThe rapid adoption of chiplet-based architectures and high-speed die-to-die interconnects primarily driven by AI/ML massive data throughput requirements and integration complexity presents significant mixed-signal verification challenges. Traditional Digital Mixed-Signal (DMS) flows lack analog fidelity, while Analog Mixed-Signal (AMS) flows struggle with scalability and manual overhead. To address these fundamental limitations, Analog Port, in close collaboration with Siemens EDA, developed a unified, top-down verification methodology designed to bridge the gap between analog fidelity and digital performance.
This innovative approach leveraging Symphony Pro, part of the Solido Simulation Suite, extends the conventional UVM based digital verification framework to mixed-signal domain, enabling a holistic verification strategy while overcoming tool fragmentation and data integrity issues. It seamlessly combines high-fidelity SPICE simulation for critical analog blocks with high-performance digital simulation for the broader system.
In this presentation, we will demonstrate how Analog Port achieved up to 26X memory savings and more than 3X performance gain for their RX and TX simulations. We will also explore this novel methodology and its implementation, showcasing how it successfully verified a complex 32 Gbps, 16-transmit/16-receive full-duplex die-to-die interface, significantly enhancing productivity, improving silicon quality, and reducing time-to-market by resolving traditional mixed-signal verification trade-offs.
This innovative approach leveraging Symphony Pro, part of the Solido Simulation Suite, extends the conventional UVM based digital verification framework to mixed-signal domain, enabling a holistic verification strategy while overcoming tool fragmentation and data integrity issues. It seamlessly combines high-fidelity SPICE simulation for critical analog blocks with high-performance digital simulation for the broader system.
In this presentation, we will demonstrate how Analog Port achieved up to 26X memory savings and more than 3X performance gain for their RX and TX simulations. We will also explore this novel methodology and its implementation, showcasing how it successfully verified a complex 32 Gbps, 16-transmit/16-receive full-duplex die-to-die interface, significantly enhancing productivity, improving silicon quality, and reducing time-to-market by resolving traditional mixed-signal verification trade-offs.
Event Type
Engineering Poster
Engineering Presentation
TimeWednesday, July 293:00pm - 3:45pm PDT
LocationDAC Pavilion, Exhibit Floor