Presentation
An Optimized Full-Chip Analog Mixed-Signal (AMS) Verification Approach for PVT Calibration in FPGA Systems
DescriptionMicrochip FPGAs feature multiple I/O banks, each configurable independently for diverse standards such as SSTL, LVSTL etc., enabling designers to mix and match signaling protocols across the same device while covering a wide frequency range. I/O banks support voltages from 0.5V to 3.3 V, including high-speed DDR PHY interfaces for LPDDR4/5 up to 3.2Gbps. Robust signal integrity across wide frequency-voltage spectrum is achieved through on die IO PVT calibration which dynamically compensates for variations in silicon process, supply voltage, temperature ensuring consistent electrical characteristics like output drive strength and termination impedance. A SAR-based digital block and analog block collaboratively manage reference currents and voltages resulting in complex mixed-signal system.
Verification of this subsystem is paramount to prevent chip-level failures. Full-chip verification challenges include multiple IO banks distributed across chip periphery and CPU-individual bank connections. Validating signal paths from CPU to farthest IO bank necessitates analyzing significant portion of the chip, leading to increased simulation runtime and memory usage.
This presentation covers PVT calibration architecture and verification strategies. It highlights how Siemens Symphony Pro optimizes debugging, reduces simulation time by ~3x, improves memory usage by ~2-3x, and streamlines regressions ensuring reliable calibration verification across diverse I/O standards and extreme PVT conditions.
Verification of this subsystem is paramount to prevent chip-level failures. Full-chip verification challenges include multiple IO banks distributed across chip periphery and CPU-individual bank connections. Validating signal paths from CPU to farthest IO bank necessitates analyzing significant portion of the chip, leading to increased simulation runtime and memory usage.
This presentation covers PVT calibration architecture and verification strategies. It highlights how Siemens Symphony Pro optimizes debugging, reduces simulation time by ~3x, improves memory usage by ~2-3x, and streamlines regressions ensuring reliable calibration verification across diverse I/O standards and extreme PVT conditions.
Event Type
Engineering Poster
Engineering Presentation
TimeTuesday, July 285:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor