Presentation
From Bottleneck to Breakthrough! Accelerating Circuit Verification Beyond Expectations
DescriptionModern system-on-chip (SoC) designs face exponential complexity with billions of geometries and hierarchical integration. Using traditional layout versus schematic (LVS) verification in early phases presents significant bottlenecks in complex SoC designs, leading to prolonged design cycles and increased costs on the entire verification flow since shorts are fundamental connectivity flaws that critically impact & bottleneck essential verification flows (e.g., ESD (electrostatic discharge), LUP (latch-up), Antenna, …etc.). A clean "shorts-free" database is a prerequisite for accurate & efficient execution of these flows.
In this paper, we are introducing a novel Targeted Short Isolation (SI) verification methodology designed to transform LVS from a bottleneck into a breakthrough. Our shift-left approach accelerates full verification flow by enabling early detection and remediation of shorts during the Floorplan and Place & Route stages. By decoupling targeted SI from full LVS complexity, designers can achieve focused remediation without the overhead of comprehensive connectivity checking. Our plug-and-play solution offers remarkable improvements, including up to 14X faster iterations and up to 90% memory savings, significantly reducing hardware requirements and improving design quality through early detection. Ultimately, this leads to a cleaner, "short-free" database across all hierarchies earlier in the design flow, enabling faster time-to-market for complex SoC designs.
In this paper, we are introducing a novel Targeted Short Isolation (SI) verification methodology designed to transform LVS from a bottleneck into a breakthrough. Our shift-left approach accelerates full verification flow by enabling early detection and remediation of shorts during the Floorplan and Place & Route stages. By decoupling targeted SI from full LVS complexity, designers can achieve focused remediation without the overhead of comprehensive connectivity checking. Our plug-and-play solution offers remarkable improvements, including up to 14X faster iterations and up to 90% memory savings, significantly reducing hardware requirements and improving design quality through early detection. Ultimately, this leads to a cleaner, "short-free" database across all hierarchies earlier in the design flow, enabling faster time-to-market for complex SoC designs.
Event Type
Engineering Poster
Engineering Presentation
TimeWednesday, July 293:00pm - 3:45pm PDT
LocationDAC Pavilion, Exhibit Floor