Presentation
Mixed Transistor Design Closure
DescriptionDesigning circuits with mix of different types transistor to achieve the right balance between performance and power has been a long used strategy. The semiconductor industry has been dealing with variability of transistors and also the extent of miscorrelations between them through skewed corners and derates. Lack of automation to fix these violations led to elongated cycletimes to address them manually. We cover a significant improvement in the prevalent methodology. Cadence's Vt skew flow can handle miscorrelations between transistors efficiently, eliminating overhead of additional STA runs. Flow is supported in Innovus and Tempus enabling optimization and timing signoff. Solution relies on a creation of bounded GBA which leads to significant pessimism in Innovus impacting optimization QoR. Signoff accuracy is not impacted by this as PBA analyzes for this effect accurately by exploring all possible skew combinations depending on the transistor types in path. The optimization challenge is overcome by employing methodology which performs VT skew analysis both in GBA and PBA modes and derives margin. Finally we present results that indicate that the Vt skew flow is able to identify paths vulnerable to transistor skew and optimize them. We have also benchmarked the analysis accuracy against SPICE
Event Type
Engineering Poster
TimeWednesday, July 293:00pm - 4:00pm PDT
LocationDAC Pavilion, Exhibit Floor