Presentation
Enhancing UVM RAL for Secure and Privileged Flash Memory Interface Verification Using Cadence AMBA VIP
DescriptionEmbedded non-volatile memory (NVM) interfaces in next-generation microcontrollers demand rigorous verification of security and privilege semantics. While the UVM Register Abstraction Layer (RAL) standardizes register access, it offers limited control over bus-level attributes required for validating secure and protected transactions. This work introduces an enhanced user adapter layer for Cadence AMBA AHB VIP, enabling verification of four distinct access modes: Privileged-Secure, Privileged-Nonsecure, Unprivileged-Secure, and Unprivileged-Nonsecure.
Our methodology integrates an extension class within the UVM RAL flow to propagate HPROT and HNONSEC attributes through reg2bus APIs, preserving abstraction while ensuring full control over secure and protected semantics. The solution extends the default adapter, which traditionally transfers data using a fixed uvm_reg_bus_op structure, by declaring an extension class handle in reg2bus. Results demonstrate improved regression stability, reduced debug effort, and systematic coverage closure without sacrificing portability. This approach strengthens verification efficiency and confidence for advanced memory interfaces in safety-critical and secure applications.
Our methodology integrates an extension class within the UVM RAL flow to propagate HPROT and HNONSEC attributes through reg2bus APIs, preserving abstraction while ensuring full control over secure and protected semantics. The solution extends the default adapter, which traditionally transfers data using a fixed uvm_reg_bus_op structure, by declaring an extension class handle in reg2bus. Results demonstrate improved regression stability, reduced debug effort, and systematic coverage closure without sacrificing portability. This approach strengthens verification efficiency and confidence for advanced memory interfaces in safety-critical and secure applications.
Event Type
Engineering Poster
TimeWednesday, July 293:00pm - 4:00pm PDT
LocationDAC Pavilion, Exhibit Floor