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Hierarchical IP Block Resizing on the Fly
DescriptionTo proof an IC concept early, critical areas of the design are synthesized using a PD synthesis flow.
IP block data may be incomplete and IP blocks may be added to a design later. Manually defining physical parameters of IP blocks based on functional requirements is an inaccurate and time-consuming step during synthesis. To enable synthesis for timing-critical subsets of incomplete IC designs, a novel PD synthesis methodology demonstrates the detection of any IP blocks of an IC design during synthesis, the scaling of IP blocks to proper sizes, and placing the respective blocks which increases the PD synthesis efficiency by 60%. The system comprises a configuration database storing IP block configuration data indexed using block-specific hierarchical identifiers. The method comprises retrieving initial configuration data for IP blocks from the configuration database using the block-specific hierarchical identifiers. A recommender system fetches existing IC configuration data and recommends sizes for blocks of the incomplete IC design. In addition, size changes for IP blocks can be provided to automatically generate updated IP block configuration data using size changes to modify the initial IP block configuration. Based on the changes, the configuration database is updated using the new IP block configuration.