Presentation
Xchip: A Guardrailed Agentic Gen-AI Front-End Flow from Intent to GDSII
DescriptionModern chip design teams are increasingly exploring Gen-AI to improve productivity in front-end design, yet practical adoption remains challenging. Most existing Gen-AI tools focus on code generation or downstream assistance, while critical front-end tasks before RTL, such as system partitioning, interface definition, and verification readiness, are still handled manually. As a result, many Gen-AI generated designs suffer from validation gaps or insufficient functional coverage, with issues only exposed during late-stage simulation or integration.
This work presents XChip, a guardrailed, agentic Gen-AI front-end design flow that enables disciplined intent-to-RTL design with a supported path to GDSII via existing backend tools. XChip treats system-level design as a first-class abstraction and introduces Natural-Level Synthesis (NLS), a design stage that bridges high-level intent and RTL by generating structured system partitions, interfaces, and constraints. Within the NLS stage, XChip incorporates Generation Rule Check (GRC) as a built-in verification mechanism, performing rule-based validation and verification at the same abstraction level.
XChip supports two complementary front-end flows: a direct NLS-to-RTL flow, and an NLS-to-HLS-to-RTL flow that integrates with existing HLS tools for incremental adoption. Experimental results show significant reductions in manual effort and iteration cycles, measured by fewer human interventions, reduced errors, and improved functional coverage, while preserving compatibility with established RTL, HLS, and backend toolchains.
This work presents XChip, a guardrailed, agentic Gen-AI front-end design flow that enables disciplined intent-to-RTL design with a supported path to GDSII via existing backend tools. XChip treats system-level design as a first-class abstraction and introduces Natural-Level Synthesis (NLS), a design stage that bridges high-level intent and RTL by generating structured system partitions, interfaces, and constraints. Within the NLS stage, XChip incorporates Generation Rule Check (GRC) as a built-in verification mechanism, performing rule-based validation and verification at the same abstraction level.
XChip supports two complementary front-end flows: a direct NLS-to-RTL flow, and an NLS-to-HLS-to-RTL flow that integrates with existing HLS tools for incremental adoption. Experimental results show significant reductions in manual effort and iteration cycles, measured by fewer human interventions, reduced errors, and improved functional coverage, while preserving compatibility with established RTL, HLS, and backend toolchains.
Event Type
Engineering Poster
TimeTuesday, July 285:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor