Presentation
Accelerating Full Flat EMIR Sign-Off in Multi-Billion Instance
DescriptionHPC applications like Datacenter, Server, AI-Training and AI-Inference application chips are Multi Billion Big-Die Designs and requires huge compute and disk requirements for simulations. Depending on the type of design architecture logic subsystems are repeated 30 to 80% of full design. Full flat simulations on such designs take ~8k to 11k cores with a peak machine memory requirement of 200TB to 300TB. Disk space requirement would be ~50TB. Hence, running Full Flat simulations are not practical as they would be taking huge compute and disk space resources. Full chip EMIR checks are important to ensure Blocks and Subsystems are well connected with RDL/Bumps and to ensure signoff is within margin. This can be done at abstract level with blocks' and subsystems' current and parasitic modelled using Reduced Order Model (ROM).On using ROM, a significant reduction is observed in run-time and disk-space used while maintaining accuracy.
Event Type
Engineering Poster
TimeWednesday, July 293:00pm - 4:00pm PDT
LocationDAC Pavilion, Exhibit Floor