Presentation
Automated Workload Analysis for Dynamic Voltage Drop Optimization and Faster Power Integrity Signoff in Complex SoC Designs
DescriptionAs power integrity margins continue to tighten in advanced nodes and 3DIC designs, identifying the true worst-case PDN stress scenarios across multiple compute tiles has become increasingly complex and time-consuming. Traditional manual exploration of block workloads and vector combinations often requires expert intervention, exhaustive simulations, and significant runtime. To address this challenge, we present an automated RedHawk-SC framework that intelligently explores Reduced Order Models(ROM)-based block workload combinations to uncover high-stress PDN conditions with minimal runtime overhead.
The proposed flow introduces a novel scenario optimization algorithm that automatically generates, ranks, and prunes workload mixes for each compute tile, capturing die-package co-analysis through integrated RedHawk-SC simulations. The framework incorporates workload intelligence to learn per-block power impact, adaptive optimization to select optimal workload pairings using a greedy exploration algorithm, and scalability across multiple domains and workload vectors. Implemented as a Python wrapper, it delivers a plug-and-play architecture supporting automation and rapid integration within existing analysis environments.
This automated flow replaces expert-driven manual analysis with a data-guided methodology that ensures accurate prediction of voltage stress regions, early detection of grid vulnerabilities, and stronger silicon correlation. The approach simplifies scenario complexity, enhances reliability coverage, and accelerates sign-off for chiplet and 3DIC architectures.
The proposed flow introduces a novel scenario optimization algorithm that automatically generates, ranks, and prunes workload mixes for each compute tile, capturing die-package co-analysis through integrated RedHawk-SC simulations. The framework incorporates workload intelligence to learn per-block power impact, adaptive optimization to select optimal workload pairings using a greedy exploration algorithm, and scalability across multiple domains and workload vectors. Implemented as a Python wrapper, it delivers a plug-and-play architecture supporting automation and rapid integration within existing analysis environments.
This automated flow replaces expert-driven manual analysis with a data-guided methodology that ensures accurate prediction of voltage stress regions, early detection of grid vulnerabilities, and stronger silicon correlation. The approach simplifies scenario complexity, enhances reliability coverage, and accelerates sign-off for chiplet and 3DIC architectures.
Event Type
Engineering Poster
TimeWednesday, July 293:00pm - 4:00pm PDT
LocationDAC Pavilion, Exhibit Floor