Presentation
A Hybrid Simulation and Formal Verification Approach for Exhaustive Interrupt and Status Flag Verification
DescriptionVerification of status flags and interrupts is critical for correct interaction between IP components, yet exhaustive validation of interrupt behavior remains challenging when relying solely on simulation-based approaches. This approach presents a hybrid simulation and formal verification methodology for interrupt and status flag verification using an interrupt Verification IP (VIP) and demonstrates its application on a Real-Time Clock (RTC) IP. Simulation-based verification is used to validate interrupt behavior under realistic programming scenarios, while formal verification is leveraged to exhaustively prove interrupt properties and corner cases that are difficult to cover in simulation. The results highlight the effectiveness of combining dynamic and formal verification through a reusable interrupt verification infrastructure to improve confidence in interrupt correctness at the IP level.
Event Type
Engineering Poster
TimeTuesday, July 285:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor
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