Presentation
Scalable EMIR Signoff for Very Large SoCs Using Reduced Order Modelling
DescriptionAt advanced process nodes, flat EMIR signoff for modern SoCs often exceeding four billion instances and 50 billion nodes faces prohibitive runtime and compute demands. This work introduces a production-proven hierarchical EMIR signoff methodology leveraging Reduced Order Model (ROM) technology to achieve scalable, resource-efficient IR/EM analysis for billion-instance systems. The proposed bottom-up flow generates compact ROMs that preserve electrical and geometric characteristics of child blocks across defined Common Connection Layers (CCL), enabling accurate hierarchical modeling without full flat complexity. Integrated automation ensures consistent ROM generation, validation, and consumption across multi-scenario, multi-PVT signoff environments. The resulting hierarchical analysis achieves near-flat accuracy with over 50% reduction in runtime and memory footprint, supporting realistic workload and packaging variations. Validation on the large scale SoC demonstrates around 75% total compute-hour reduction, 55% disk space savings and 35% memory improvement.
This methodology has been successfully deployed in production for next-generation Arm SoCs, enabling faster turnaround and efficient compute utilization in both on-premise and hybrid cloud environments. The flow establishes a scalable, practical, and high-fidelity EMIR signoff paradigm transforming hierarchical verification for large-scale, advanced-node SoCs.
This methodology has been successfully deployed in production for next-generation Arm SoCs, enabling faster turnaround and efficient compute utilization in both on-premise and hybrid cloud environments. The flow establishes a scalable, practical, and high-fidelity EMIR signoff paradigm transforming hierarchical verification for large-scale, advanced-node SoCs.
Event Type
Engineering Poster
TimeWednesday, July 293:00pm - 4:00pm PDT
LocationDAC Pavilion, Exhibit Floor