Presentation
Novel Approach to Signoff Large MRAM Memory IP Using Hierarchical Flow
DescriptionAt SOC level, customer requires comprehensive electrical views, of the memory IP we design, to support Power and Reliability sign-off. Generating APL models requires waveform database (FSDB) from the spice simulation of the IP. As IP size is very huge, full extracted macro simulations are not practical. So, we have used a hierarchical approach using block level simulations, without losing accuracy. We are able to generate model in reasonable runtime. we compared the results from Hierarchical approach against results from a flat run for the smallest IP, and the results are comparable.
Event Type
Engineering Poster
TimeTuesday, July 285:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor