Presentation
An Adaptive Dynamic Power Reduction Technique for Digital Filters
DescriptionDigital FIR filters are typically designed for worst-case full-scale input precision, resulting in unnecessary dynamic power dissipation when processing low-amplitude signals. This paper introduces an adaptive technique that tracks real-time signal dynamic range and selectively disables toggling of sign-extended bits in datapath registers. By gating both data and clock for these redundant bits, the approach significantly reduces switching activity without impacting filter functionality or performance. Demonstrated on a 20-tap FIR filter in 28nm FDSOI technology, the proposed architecture achieved over 7% total power savings for a wideband OFDM signal with -24 dB input amplitude. The solution is fully digital, incurs minimal hardware overhead, and is easily deployable across existing filter architectures and technologies. Furthermore, it is scalable to other shift-register-based structures such as delay chains and FIFOs, making it a practical and efficient method for dynamic power reduction in contemporary signal processing systems.
Event Type
Engineering Poster
TimeTuesday, July 285:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor