Presentation
A Compact Digital IP for FMCW Chirp Linearity Monitoring in Automotive Radar Systems
DescriptionAutomotive radar systems rely on highly linear FMCW chirp signals to ensure accurate distance and velocity measurements for ADAS applications. Deviations in chirp linearity can compromise radar performance and violate functional safety standards. This paper presents a compact, all-digital IP for real-time chirp linearity monitoring integrated within the radar transmitter subsystem. The proposed solution leverages zero-crossing alignment between the chirp signal and an on-chip reference clock to compute instantaneous frequency slope deviations without requiring dedicated high-frequency clocks. The architecture includes counters, edge overlap detection, and an error computation engine, demonstrates detection of minor deviations as low as 0.001% across a 10 μs chirp duration. Implemented entirely in digital logic, the IP is technology-independent, incurs less than 5% area overhead, and operates with any available on-chip clock source. This scalable, low-cost solution enhances radar transmitter reliability and supports compliance with automotive safety standards, making it ideal for integration into next-generation radar SoCs.
Event Type
Engineering Poster
TimeTuesday, July 285:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor