Presentation
Revisiting PDN at the MOL Boundary: A Placement-Aware Power Delivery Flow
DescriptionAt advancded nodes, aggressive cell height scaling has made lower metal routing resources a primary limiter for block-level PPA, as these layers are simultaneously demanded by signal routing, pin access, and power delivery. While adding more routing layers can increase overall capacity, the benefit diminishes with deeper metal stacks, leaving lower metals as the most performance-critical and congested resources.
This work revisits power delivery at the middle-of-line (MOL) boundary and proposes a placement-aware MOL-PDN integration flow that redistributes PDN burden away from lower metals without altering the conventional P&R flow. The proposed approach introduces MOL-level PDN segments during pre-placement and further adapts them after routing, enabling effective lower-metal resource reallocation while preserving the conventional physical design methdology.
Experiments on a large ARM CPU sub-block show that the proposed MOL-PDN flow achieves up to 0.6% frequency improvement and up to 1.5% total wirelength reduction compared to a conventional lower-metal PDN scheme. Static IR behavior is maintained, while increased dynamic IR sensitivity is observed under signoff worst-case conditions.
This work revisits power delivery at the middle-of-line (MOL) boundary and proposes a placement-aware MOL-PDN integration flow that redistributes PDN burden away from lower metals without altering the conventional P&R flow. The proposed approach introduces MOL-level PDN segments during pre-placement and further adapts them after routing, enabling effective lower-metal resource reallocation while preserving the conventional physical design methdology.
Experiments on a large ARM CPU sub-block show that the proposed MOL-PDN flow achieves up to 0.6% frequency improvement and up to 1.5% total wirelength reduction compared to a conventional lower-metal PDN scheme. Static IR behavior is maintained, while increased dynamic IR sensitivity is observed under signoff worst-case conditions.
Event Type
Engineering Poster
TimeWednesday, July 293:00pm - 4:00pm PDT
LocationDAC Pavilion, Exhibit Floor
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