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A Novel Methodology for Automated LVS Rule Deck Verification: Truth Table and Device Extraction Qualification

DescriptionModern semiconductor fabrication faces an escalating verification challenge as technology nodes shrink to 3nm and beyond, where Layout Versus Schematic (LVS) verification complexity has grown exponentially. Today's LVS must go beyond comparing Schematic and Layout designs; it must extract R/C values for hundreds of devices, perform parasitic extraction (PEX), and analyze complex CAD layer interactions. At 3nm nodes, device extraction requires 30 to 50 CAD layers per device due to Mask Data Preparation (MDP) demands, making manual verification infeasible. This paper presents a novel automated Device Extraction Quality Assurance (QA) framework integrating three verification engines: Truth Table Checker, Compare Checker, and Device Extraction QA. The workflow ensures device extraction is properly performed as described by process development, extracting layouts from seed layers and supplying devices to SPICE netlists for simulation-based verification. Validated across technologies from 8-12 inch legacy processes to 3nm nodes, the framework enables early detection of truth table errors and parasitic device extraction issues through automated parameter qualification. The truth table checker flow has dramatically reduced turn-around time to rule deck release while significantly improving quality. With average runtimes under 30 minutes, qualification engineers receive comprehensive reports clearly indicating where attention is needed, enabling rapid issue resolution and high-confidence PDK releases.

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