Presentation
Novel Methodology for in Context Blockage Modification for High-Speed Global Clock Routing
DescriptionModern microprocessors grow increasingly complex with each generation, making hierarchical design essential for managing scale and complexity. In Physical Design, this translates into processing smaller building blocks from RTL to GDS, which are later integrated at higher levels. A critical aspect is constructing the high-speed global clock network on a hierarchical clock grid.
Traditionally, this process begins by defining blockages for global clock grid at the top level, followed by carving out blockages for smaller blocks. The global clock is then routed within these reserved areas and combined across levels. To ensure correctness, buildability, and functionality, global clock checks are performed both on individual blocks and at the highest level. However, this approach is time-intensive and heavily reliant on expert knowledge for defining routing blockages.
To address these challenges, the IBM z-Microprocessor team has developed an automated, in-context reservation modification technique that enables building a functional global clock from the ground up. This innovation significantly reduces dependency on manual expertise and accelerates the design process, improving efficiency and scalability for future microprocessor designs.
Traditionally, this process begins by defining blockages for global clock grid at the top level, followed by carving out blockages for smaller blocks. The global clock is then routed within these reserved areas and combined across levels. To ensure correctness, buildability, and functionality, global clock checks are performed both on individual blocks and at the highest level. However, this approach is time-intensive and heavily reliant on expert knowledge for defining routing blockages.
To address these challenges, the IBM z-Microprocessor team has developed an automated, in-context reservation modification technique that enables building a functional global clock from the ground up. This innovation significantly reduces dependency on manual expertise and accelerates the design process, improving efficiency and scalability for future microprocessor designs.
Event Type
Engineering Poster
TimeTuesday, July 285:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor
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