Presentation
ARTEMIS: Agentic AI for EDA
DescriptionFront-end RTL verification workflows consume significant compute resources and engineer time, with Verilog simulations often failing due to syntax errors, testbench issues, or configuration problems detected only after resource consumption. Traditional workflow management lacks predictive intelligence to prevent this waste.
This presentation introduces ARTEMIS (Automated RTL Testing & Error Management Intelligent System), a production-deployed multi-agent AI architecture that optimizes front-end verification workflows through intelligent error detection. ARTEMIS employs four specialized agents working collaboratively: Debug Agent (error identification), Supervisor Agent (resource orchestration), Scheduler Agent (regression test sequencing), and Job Analysis Agent (real-time monitoring). The system integrates with Verilog and industry-standard schedulers through Model Context Protocol servers.
The intelligent error detection system analyzes iverilog output patterns to identify syntax errors, module instantiation issues, and testbench problems before they consume compute resources. When failures are predicted, the system automatically terminates jobs and releases resources.
Production deployment metrics demonstrate 15-25% reduction in compute costs and 45% reduction in debugging time. This presentation chronicles the journey from award-winning prototype to production MLP with actionable implementation guidance for EDA workflows
This presentation introduces ARTEMIS (Automated RTL Testing & Error Management Intelligent System), a production-deployed multi-agent AI architecture that optimizes front-end verification workflows through intelligent error detection. ARTEMIS employs four specialized agents working collaboratively: Debug Agent (error identification), Supervisor Agent (resource orchestration), Scheduler Agent (regression test sequencing), and Job Analysis Agent (real-time monitoring). The system integrates with Verilog and industry-standard schedulers through Model Context Protocol servers.
The intelligent error detection system analyzes iverilog output patterns to identify syntax errors, module instantiation issues, and testbench problems before they consume compute resources. When failures are predicted, the system automatically terminates jobs and releases resources.
Production deployment metrics demonstrate 15-25% reduction in compute costs and 45% reduction in debugging time. This presentation chronicles the journey from award-winning prototype to production MLP with actionable implementation guidance for EDA workflows
Event Type
Engineering Poster
TimeTuesday, July 285:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor