Presentation
Pipeline-Based Denial of Service Attacks on Embedded RISC-V Core-Based Systems
DescriptionEmbedded RISC-V processors are often deployed in real-time and safety-critical systems due to their simplicity, predictability, and open architecture. However, these systems remain vulnerable to performance degradation caused by microarchitectural resource contention. This work investigates pipeline-based Denial of Service attacks on in-order embedded RISC-V cores, demonstrating how malicious firmware can exploit pipeline structures to significantly degrade system performance without violating functional correctness or privilege isolation. We design and implement representative attack primitives targeting instruction cache thrashing, long dependency chains, and branch misprediction, and compare them against baseline workloads. Both attack and baseline functions are simulated on an RTL-level RISC-V core. Performance counters such as cycle count, instructions retired, fetch stalls, and branch activity are logged and analyzed to quantify the performance degradation. Experimental results show performance degradation of up to 27% compared to baseline execution, with substantial amplification in instruction fetch stalls and pipeline inefficiencies. Our findings highlight the feasibility of user-mode pipeline-based DoS attacks in embedded RISC-V systems and motivate the need for lightweight mitigation strategies. We discuss potential defenses, including cache partitioning, performance-counter-based monitoring, and speculation throttling, and outline future research directions for secure and predictable RISC-V designs.
Event Type
Engineering Poster
TimeMonday, July 275:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor
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