Presentation
Early, Efficient and Scalable Parasitic-Aware Layout Design Methodology for High-Precision ICs
DescriptionDue to the increasing size and complexity of high-performance integrated circuits (ICs), especially in advanced technology nodes, the influence of parasitics on the layout has become dominant. Traditional signoff tools and internal scripts often suffer from slow execution, challenging maintenance, and insufficient precision, which limits their effectiveness in addressing the stringent requirements of precision ICs.
To overcome these limitations, a systematic flow for early IC layout parasitic analysis has been developed for quick and efficient detection and debug of parasitic violations. Our shift-left methodology establishes a framework for defining constraints upfront on all critical design nets, enables comparison of multiple layout revisions and provides unique capabilities for verifying large top-level design hierarchies - ensuring robust coverage across diverse design teams and technology nodes.
The flow's scalability allows its adoption for various design styles, facilitating early detection, debugging, and resolution of even minute parasitic violations that would otherwise require lengthy simulation cycles. As a result, design time is significantly reduced by minimizing iterative simulation runs, leading to substantial savings in hardware resources and software license requirements for simulation tools. This systematic early parasitic analysis flow represents a transformative advancement for precision IC development, delivering enhanced design quality, reliability, and productivity.
To overcome these limitations, a systematic flow for early IC layout parasitic analysis has been developed for quick and efficient detection and debug of parasitic violations. Our shift-left methodology establishes a framework for defining constraints upfront on all critical design nets, enables comparison of multiple layout revisions and provides unique capabilities for verifying large top-level design hierarchies - ensuring robust coverage across diverse design teams and technology nodes.
The flow's scalability allows its adoption for various design styles, facilitating early detection, debugging, and resolution of even minute parasitic violations that would otherwise require lengthy simulation cycles. As a result, design time is significantly reduced by minimizing iterative simulation runs, leading to substantial savings in hardware resources and software license requirements for simulation tools. This systematic early parasitic analysis flow represents a transformative advancement for precision IC development, delivering enhanced design quality, reliability, and productivity.
Event Type
Engineering Poster
TimeTuesday, July 285:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor