Presentation
Accelerating IR and Timing Convergence with Revolutionary IR-ECO
DescriptionComplex applications (such as AI & HPC) and advanced tech nodes are driving a dramatic increase in design scale and complexity. It's currently impractical to construct a robust power delivery network (PDN) by consuming a large amount of design resources and the higher local cell density causes worse voltage drop(IR) violations than ever before. At the same time, the margin of the process is decreasing continuously, the influence of voltage drop on timing is becoming increasing prominent. Therefore, it becomes crucial to establish the correlation between IR and timing to avoid over-fixing.
In traditional flow,
§ We fix IR violations by fixing thousands of violation instances(victims). However, this approach has a low profit. It takes multiple manual iterations to resolve the violations, because the root cause of the violations(aggressors) is not identified.
§ The impact on timing cannot be considered during the manual IR violation fix cycles. Meanwhile, an instance with IR issue is usually also an instance that is sensitive to the timing. In this case, we finally need to perform a hard tradeoff between IR and timing.
§ Separated IR and Timing ECOs are very time consuming, costly and always posed significant challenges for design closure within tape-out timelines.
To minimize iteration counts and design changes, avoid timing degradation or chip failure, an automated late-stage timing-aware IR fix methodology is proposed here. The joint IR-ECO flow ensures seamless communication between the golden ECO tool PrimeClosure and golden IR/EM analysis tool RedHawk-SC, enables accurate identification of root cause aggressors, provides immediate feedback on the voltage impact of ECO operations proposed by PrimeClosure, and automatically fixes IR violations without timing hurt.
In our design, IR-ECO can fix over 60% of signoff-stage IR violations within a few hours, and introducing few/no negative impact on timing, which is very important for timing- critical blocks. Minimum number of instances changed by addressing aggressors. Fewer design change operations and minimum iterations can save several weeks of iteration period than traditional flow. This offering better PPA and significantly boosts the time to tape out.
keywords : IR-ECO, IR-timing closure, aggressor analytics, timing-aware IR fix
In traditional flow,
§ We fix IR violations by fixing thousands of violation instances(victims). However, this approach has a low profit. It takes multiple manual iterations to resolve the violations, because the root cause of the violations(aggressors) is not identified.
§ The impact on timing cannot be considered during the manual IR violation fix cycles. Meanwhile, an instance with IR issue is usually also an instance that is sensitive to the timing. In this case, we finally need to perform a hard tradeoff between IR and timing.
§ Separated IR and Timing ECOs are very time consuming, costly and always posed significant challenges for design closure within tape-out timelines.
To minimize iteration counts and design changes, avoid timing degradation or chip failure, an automated late-stage timing-aware IR fix methodology is proposed here. The joint IR-ECO flow ensures seamless communication between the golden ECO tool PrimeClosure and golden IR/EM analysis tool RedHawk-SC, enables accurate identification of root cause aggressors, provides immediate feedback on the voltage impact of ECO operations proposed by PrimeClosure, and automatically fixes IR violations without timing hurt.
In our design, IR-ECO can fix over 60% of signoff-stage IR violations within a few hours, and introducing few/no negative impact on timing, which is very important for timing- critical blocks. Minimum number of instances changed by addressing aggressors. Fewer design change operations and minimum iterations can save several weeks of iteration period than traditional flow. This offering better PPA and significantly boosts the time to tape out.
keywords : IR-ECO, IR-timing closure, aggressor analytics, timing-aware IR fix
Event Type
Engineering Poster
TimeTuesday, July 285:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor