Presentation
Accelerating CPU Design in Advanced Nodes with AI-Powered Floor Planning and VT Optimization
DescriptionAs technology nodes scale into the angstrom regime, design complexity has surged due to stringent performance, power, and area (PPA) targets and the need to manage diverse cell libraries across multiple PVT corners. Achieving optimal cell selection, macro placement, and layer distribution under these conditions is highly challenging, making manual tuning impractical given tight timing closure, power budgets, VT proliferation, and floorplan sensitivity. Automation is now essential to enable systematic design space exploration and maintain competitiveness.
This paper presents an AI-driven approach to automate floorplanning and VT optimization for macro-dominated, high-frequency CPU designs in sub-nanometer nodes. The proposed solution integrates VT-Optimizer (VT-Opt), which tunes multi-VT flows by generating adaptive VT recipes and validating them through full-flow runs, and FP-Opt, which explores alternative floorplans by adjusting bounding boxes, aspect ratios, and macro placements while targeting utilization, congestion, timing, and power. Optimal configurations are selected based on full-flow evaluations, followed by PPA optimization to achieve best-in-class results.
The methodology significantly reduces design turnaround time, mitigates risk, and improves PPA, demonstrating its effectiveness for next-generation CPU designs.
This paper presents an AI-driven approach to automate floorplanning and VT optimization for macro-dominated, high-frequency CPU designs in sub-nanometer nodes. The proposed solution integrates VT-Optimizer (VT-Opt), which tunes multi-VT flows by generating adaptive VT recipes and validating them through full-flow runs, and FP-Opt, which explores alternative floorplans by adjusting bounding boxes, aspect ratios, and macro placements while targeting utilization, congestion, timing, and power. Optimal configurations are selected based on full-flow evaluations, followed by PPA optimization to achieve best-in-class results.
The methodology significantly reduces design turnaround time, mitigates risk, and improves PPA, demonstrating its effectiveness for next-generation CPU designs.
Event Type
Engineering Poster
TimeTuesday, July 285:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor