Presentation
Integrated Design Approach for Robust and Area-Efficient IO Ring in Advanced Process Nodes
DescriptionIn advanced semiconductor technology nodes, designing a robust and area efficient I/O ring poses significant challenges due to tighter design margins, increased integration density, and stringent reliability requirements. To cultivate this efficiency requires a methodology for high performance and robustness while maintaining efficient area utilization in I/O ring design for advanced process nodes. This paper presents an integrated design approach that optimizes layout, and system-level parameters to achieve high performance robustness by achieving area efficient I/O ring. The integrated approach results in significantly reduction in I/O ring area and power routing complexity while maintaining compliance with ESD, electromigration, and noise tolerance specifications.
Event Type
Engineering Poster
TimeTuesday, July 285:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor