Presentation
Next-Generation 3DIC STCO: AI-Enabled PPA and Cost Optimization Through IEEE P3537 3Dblox
DescriptionChiplet based 3D disaggregation is the future of chip design that brings many benefits such as better PPA (power, performance, area) and cost. The optimal chiplet stack, however, can be difficult to determine given the large number of design parameters to consider. Common questions to encounter could be which process technology to use for each chiplet, and how to partition the design on each chiplet. In this work, we demonstrate an AI-driven system-technology co-optimization (STCO) platform that leverages IEEE P3537 3Dblox to define 3D chiplet stacks based on the available process technologies. This methodology automatically experiments with hundreds of different combinations and permutations of process technologies, die sizes, and aspect ratios for each chiplet, as well as optimizing for heterogenous 3D design partitioning PPA in each 3DIC stack to obtain the best timing, power, IR, thermal, and other key metrics. The methodology uses user-defined relative wafer costs between process technologies to optimize for total die costs of each 3DIC stack instead of simple area metrics. With this AI-driven methodology, we automated the optimization of 3DIC process technology selection, 3D design partitioning with placement and bump assignment, and 3D design PPA and cost exploration in one single platform.
Event Type
Engineering Poster
TimeMonday, July 275:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor
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