Presentation
Design Verification Automation (DVA) for PCB Signal and Power Integrity
DescriptionModern PCB designs contain thousands of signal nets operating up to multi-GHz frequencies, coupled with components requiring tight supply tolerances and increasing power demands through complex power distribution networks. These designs require comprehensive signal and power integrity (SIPI) verification to achieve first-pass design success and minimize board iterations. However, traditional SIPI workflows create significant bottlenecks, requiring extensive electromagnetic (EM) extraction and simulation setup expertise and manual intervention across multiple tool interfaces. Conventional analysis consumes weeks to months per design iteration while limiting verification to specialized engineers—a critical constraint for organizations.
This work presents an integrated SIPI verification framework that automates the complete workflow from EM extraction through circuit simulation to performance evaluation. The methodology introduces: (1) automated mesh generation and solver configuration reducing setup time from hours to minutes, (2) template-based circuit testbenches enabling seamless SPICE and IBIS model integration with extracted parasitic networks, and (3) automated post-processing with customizable pass/fail criteria and standardized reporting templates.
Validation across several production board designs demonstrates reduction in revision time from 24% to 3% while achieving 100% first-pass prototype success rate. This framework enables engineers with basic SIPI knowledge to perform comprehensive verification and optimization, expanding team capacity and design coverage.
This work presents an integrated SIPI verification framework that automates the complete workflow from EM extraction through circuit simulation to performance evaluation. The methodology introduces: (1) automated mesh generation and solver configuration reducing setup time from hours to minutes, (2) template-based circuit testbenches enabling seamless SPICE and IBIS model integration with extracted parasitic networks, and (3) automated post-processing with customizable pass/fail criteria and standardized reporting templates.
Validation across several production board designs demonstrates reduction in revision time from 24% to 3% while achieving 100% first-pass prototype success rate. This framework enables engineers with basic SIPI knowledge to perform comprehensive verification and optimization, expanding team capacity and design coverage.
Event Type
Engineering Poster
TimeTuesday, July 285:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor
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