Presentation
A Simple and Predictable Solution for Early Full-Chip LVS Convergence
DescriptionFor Large designs with multiple levels of hierarchies, predicting LVS convergence is very challenging if there are power and ground shorts and opens especially across hierarchies, as its debug could be time consuming and iterative. Also, it is difficult to identify all integration issues at next hierarchy level if any partition is LVS dirty. There are inherent disadvantages in traditional techniques such as black box LVS and destructive cleanup approach that can enable hierarchical level LVS run. To overcome these shortcomings, a simple and efficient solution which can be implemented at any stage of the partition's APR flow from floorplan to route, is described. In this solution critical interface details like Power-Ground network, global clock and signal routes which are pushed down to partitions, hard macros and partition ports are retained and are made LVS clean using this automated flow. This solution was wildly used for many partitions to identify and fix LVS issues accurately early on in multiple projects and enabled timely SoC tape-outs. This solution enabled seamless integration of late-coming partitions, as all the risks with integration were identified and fixed upfront.
Event Type
Engineering Poster
TimeTuesday, July 285:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor