Presentation
A Novel Design Approach for Optimized EMC and Thermal Performance in Next-Generation Automotive Applications
DescriptionWith the ongoing advancement of automotive intelligence, vehicles are incorporating an increasing number of semiconductor chips to improve efficiency and functionality. This technological progression results in elevated current levels across automotive systems, leading to two key physical challenges: electromagnetic compatibility (EMC) and thermal management. Properly managing these factors is crucial for ensuring system stability and reliability.
However, simultaneously addressing EMC and thermal effects is complex, as their respective physical impacts and design requirements are often conflicting. This complexity extends the design cycle needed to achieve a suitable balance between EMC and thermal considerations that meets chip specifications. To address this challenge, Denso and Siemens EDA have partnered to develop an automated optimization workflow by integrating Siemens' Solido Simulation Suite, HEEDS, and FLOEFD. This approach efficiently determines optimal design solutions for both EMC and thermal performance.
Utilizing this innovative workflow can reduce design timelines by up to 68% and decrease physical area requirements by as much as 20%. These improvements significantly accelerate time-to-market and lower costs associated with circuit design for automotive applications.
However, simultaneously addressing EMC and thermal effects is complex, as their respective physical impacts and design requirements are often conflicting. This complexity extends the design cycle needed to achieve a suitable balance between EMC and thermal considerations that meets chip specifications. To address this challenge, Denso and Siemens EDA have partnered to develop an automated optimization workflow by integrating Siemens' Solido Simulation Suite, HEEDS, and FLOEFD. This approach efficiently determines optimal design solutions for both EMC and thermal performance.
Utilizing this innovative workflow can reduce design timelines by up to 68% and decrease physical area requirements by as much as 20%. These improvements significantly accelerate time-to-market and lower costs associated with circuit design for automotive applications.
Event Type
Engineering Poster
Engineering Presentation
TimeTuesday, July 285:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor