Presentation
Bridging Hardware-Software Abstraction In UVM Verification
DescriptionIn advanced verification environments, standard UVM monitors may not offer enough flexibility or abstraction to capture and relay all relevant hardware events to the testbench. To solve this, a standardized mechanism is needed that allows smooth, event-driven communication from hardware interfaces to the UVM environment. This is especially crucial when the testbench must respond to complex hardware events—such as status changes, signal transitions, or protocol-specific conditions—and use these events to drive scoreboards, perform checks, or trigger reference model transactions. By adding proxy objects that serve as intermediaries between the hardware (HDL) and software (UVM) domains, the testbench can respond to hardware events in a modular and reusable way, reducing dependence on direct signal polling and improving maintainability. This approach is generally applicable to any hardware signal that needs to stay synchronized with the UVM environment.
Event Type
Engineering Poster
TimeMonday, July 275:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor