Presentation
Breaking the Simulation Wall – Practical Acceleration for Pre-Silicon Validation
DescriptionNext-generation SoCs demand robust and high-confidence DDR subsystem verification, yet traditional simulation struggles to keep pace. Long-duration DDR behaviors—such as training loops, refresh cycles, retention checks, and hours of sustained traffic—consume excessive simulation time and slow down project velocity. These time-intensive patterns often stall coverage closure, push out debug windows, and delay subsystem readiness.
This work showcases a high-performance verification acceleration strategy using the Siemens Veloce Strato CS hardware emulation platform to remove these bottlenecks. By transitioning existing UVM stimulus into an emulation-optimized transactor environment, the flow executes long-running DDR workloads at speed order of magnitude faster while maintaining cycle-accurate behavior and full debug correlation. The result is faster iteration, increased test throughput, and earlier discovery of timing-sensitive issues that rarely surface in conventional simulation schedules.
Key highlights include an optimized DDR command/data transactor architecture for emulation, transparent reuse of simulation sequences, and targeted debug techniques purpose-built for hardware-assisted verification. This accelerated DDR flow enables teams to run extensive, hours-to-days traffic profiles within practical timelines—transforming verification productivity and delivering higher confidence in subsystem quality ahead of tape-out.
This work showcases a high-performance verification acceleration strategy using the Siemens Veloce Strato CS hardware emulation platform to remove these bottlenecks. By transitioning existing UVM stimulus into an emulation-optimized transactor environment, the flow executes long-running DDR workloads at speed order of magnitude faster while maintaining cycle-accurate behavior and full debug correlation. The result is faster iteration, increased test throughput, and earlier discovery of timing-sensitive issues that rarely surface in conventional simulation schedules.
Key highlights include an optimized DDR command/data transactor architecture for emulation, transparent reuse of simulation sequences, and targeted debug techniques purpose-built for hardware-assisted verification. This accelerated DDR flow enables teams to run extensive, hours-to-days traffic profiles within practical timelines—transforming verification productivity and delivering higher confidence in subsystem quality ahead of tape-out.
Event Type
Engineering Poster
Engineering Presentation
TimeTuesday, July 285:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor