Presentation
Liberty-Based Profiling for IP Benchmarking
DescriptionFoundational IPs like standard cells, IOs and memories are vital for SoC development, with the Liberty (.lib) format central to capturing timing, power, and statistical variation. However, modern libraries are increasingly complex and foundry-specific, posing significant challenges for IP evaluation and selection.
Key hurdles include:
- High Cell Count: Advanced libraries contain thousands of cells, each with multiple timing arcs and conditions.
- Formatting Inconsistencies: Variations in naming conventions, data models, and variants across IP providers complicate analysis.
- Iterative PPA Estimation: Traditional Power, Performance, and Area (PPA) assessment is a time-consuming, iterative process involving Synthesis, Static Timing Analysis (STA), and Place & Route.
- Early Selection Impact: Choosing the wrong library early can lead to timing violations, power inefficiencies, area overruns, and costly redesign cycles.
To address these issues, we present a methodology for Liberty-based profiling to enable early, aligned analysis of IP views, including support for statistical models (LVF). It facilitates the comparison of timing and power trends across different variants (e.g., threshold voltage i.e. vt corners, base vs. derived cells), streamlining the library selection process.
Key hurdles include:
- High Cell Count: Advanced libraries contain thousands of cells, each with multiple timing arcs and conditions.
- Formatting Inconsistencies: Variations in naming conventions, data models, and variants across IP providers complicate analysis.
- Iterative PPA Estimation: Traditional Power, Performance, and Area (PPA) assessment is a time-consuming, iterative process involving Synthesis, Static Timing Analysis (STA), and Place & Route.
- Early Selection Impact: Choosing the wrong library early can lead to timing violations, power inefficiencies, area overruns, and costly redesign cycles.
To address these issues, we present a methodology for Liberty-based profiling to enable early, aligned analysis of IP views, including support for statistical models (LVF). It facilitates the comparison of timing and power trends across different variants (e.g., threshold voltage i.e. vt corners, base vs. derived cells), streamlining the library selection process.
Event Type
Engineering Poster
Engineering Presentation
TimeMonday, July 275:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor