Presentation
Identifying Weakest Links: A Cell Scoring Metric for Robust Design in Advanced Nodes
DescriptionAdvanced-node standard cell libraries often include thousands of cells characterized across 50+ PVT corners.
Identifying high-risk cells, those most prone to LVF variation or exhibiting abnormal trends across drive strength, VT, or gate length, is critical for:
- Guiding PnR and STA tools to apply Don't Use / Don't Touch (DUDT) constraints
- Estimating SoC-level PPA impact
- When such cells are used, including derates
- Prioritizing cells or arcs for redesign and improvement.
We propose a cell scoring methodology that ranks cells based on Liberty-derived parameters such as nominal delay combined with LVF sigma variation, leakage power, CCSP dynamic current (peak and area), CCSN noise susceptibility and more.
Through the automated ranking system, cells with worst LVF spread and CCS anomalies were quickly identified, which provided for easy analysis, guidance for SOC designers, and subsequent recommendations to aide on improvements at the cell level.
Alongside this key value, the work empowered NXP to improve efficiency of their QA at a rate of 1.5x when compared to their previous manual methodologies for ranking.
Identifying high-risk cells, those most prone to LVF variation or exhibiting abnormal trends across drive strength, VT, or gate length, is critical for:
- Guiding PnR and STA tools to apply Don't Use / Don't Touch (DUDT) constraints
- Estimating SoC-level PPA impact
- When such cells are used, including derates
- Prioritizing cells or arcs for redesign and improvement.
We propose a cell scoring methodology that ranks cells based on Liberty-derived parameters such as nominal delay combined with LVF sigma variation, leakage power, CCSP dynamic current (peak and area), CCSN noise susceptibility and more.
Through the automated ranking system, cells with worst LVF spread and CCS anomalies were quickly identified, which provided for easy analysis, guidance for SOC designers, and subsequent recommendations to aide on improvements at the cell level.
Alongside this key value, the work empowered NXP to improve efficiency of their QA at a rate of 1.5x when compared to their previous manual methodologies for ranking.
Event Type
Engineering Poster
Engineering Presentation
TimeTuesday, July 285:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor