Presentation
Enhancing Thermal Aware Optimization for 3D Heterogeneous Chiplets Integration: A System-Technology Co-Optimization (STCO) Perspective on Spatial-Temporal Temperature Uniformity
DescriptionAnalog Compute-In-Memory performance in 3D heterogeneous chiplet integration is highly sensitive to spatial temperature gradients and temporal temperature fluctuations. Conventional thermal sign-off based on the maximum junction temperature is insufficient for ensuring the memory algorithmic precision across diverse operational phases. This study proposes a System-Technology Co-Optimization (STCO) framework featuring Thermal Avoidance and Thermal Compensation strategies to enhance spatial-temporal temperature uniformity. The approach synergizes hardware-level spatial optimization, such as selective transistor density reduction and controllable heating element deployment, with software-level temporal regulation, such as load-rate modulation and dummy workflow supplement. The proposed strategies are validated by the thermal simulations of an 8-layer memory stack on a high-power SoC utilizing a granular Chip Thermal Model (CTM). The results demonstrate that the SoC-adjacent memory die has the highest thermal risk and the strategies can reduce its spatial temperature gradient by up to 25%. This work provides a practical, early-stage STCO solution for maintaining memory reliability and functional integrity in advanced 3D integrated systems.
Event Type
Engineering Poster
TimeMonday, July 275:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor