Presentation
Matching Constraint Driven Synchronous Array Implementation for High-Performance ADCs
DescriptionAdvanced Analog-to-Digital Converter (ADC) designs at 28nm and below demand stringent layout symmetry to ensure parasitic balance and electrical integrity. Conventional unit-cell based approaches for OpAmp arrays rely on manual placement and routing, which fail to preserve logical connectivity and require repetitive Engineering Change Orders (ECO) and Design Rule Check (DRC) corrections across multiple cells. This paper introduces a Design Intent-driven Group Array methodology that enables synchronous placement and routing of matched devices for high-performance ADCs. The proposed flow leverages Group Array constructs to replicate edits globally, maintain connectivity, and support operations such as stretch, chop, and cloning directly on the layout canvas. Nested Group Arrays further optimize symmetry for half-cell structures, while integrated routing assistants complete top-level interconnects. Experimental results demonstrate a 30% reduction in turnaround time (TAT) and significant improvement in DRC/ECO efficiency compared to conventional methods. By combining constraint-driven automation with synchronous array cloning, this approach delivers scalable, manufacturable, and electrically robust layouts for advanced-node ADC implementations.
Event Type
Engineering Poster
TimeMonday, July 275:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor