Presentation
AI-Enabled Flow for Silicon Area Reduction and Design Closure
DescriptionAbstract—Artificial Intelligence (AI) has emerged as a transfor-
mative technology in electronic design automation (EDA) flows,
enabling significant improvements in power, performance, and
area (PPA) metrics. This paper explores the critical role of AI-
driven techniques in optimizing semiconductor design processes,
highlighting how intelligent algorithms can automate decision-
making, predict optimal design parameters, and effectively re-
duce silicon area. By integrating AI into the design flow, users can
achieve enhanced PPA trade-offs, minimize manual intervention,
and accelerate time-to-market. The study demonstrates practical
methodologies and case studies illustrating how AI empowers
designers to optimize chip layouts, improve resource utilization,
and achieve superior silicon efficiency.
Index Terms—EDA, PPA, Artificial Intelligence, Floorplanning,
Silicon Area Reduction
mative technology in electronic design automation (EDA) flows,
enabling significant improvements in power, performance, and
area (PPA) metrics. This paper explores the critical role of AI-
driven techniques in optimizing semiconductor design processes,
highlighting how intelligent algorithms can automate decision-
making, predict optimal design parameters, and effectively re-
duce silicon area. By integrating AI into the design flow, users can
achieve enhanced PPA trade-offs, minimize manual intervention,
and accelerate time-to-market. The study demonstrates practical
methodologies and case studies illustrating how AI empowers
designers to optimize chip layouts, improve resource utilization,
and achieve superior silicon efficiency.
Index Terms—EDA, PPA, Artificial Intelligence, Floorplanning,
Silicon Area Reduction
Event Type
Engineering Poster
TimeTuesday, July 285:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor