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Low Power Optimization Through Fast and Accurate Time-Based Power Analysis

DescriptionThis paper introduces a low power optimization flow based on time-driven power analysis to reduce dynamic power. Our approach is to integrate simulation-based toggle rate estimation, which was not actually introduced into commercial tools due to runtime and limited input vectors despite high accuracy, into real-world implementation. We replace the probabilistic approach using Switching Activity Interface Format (SAIF), which is commonly used in commercial tools for toggle rate estimation of combinational logic gates, with time-driven simulation using Fast Signal Data Base (FSDB), and evaluate the effects of power, timing, and runtime. In addition, to solve the runtime increase, which is the most critical limitation of time-based flow, we propose Activity Window Profiling, an innovative approach that applies a partial duration representing the entire duration of the FSDB. Our FSDB-based flow with activity window profiling is practically implemented in the state-of-the-art synthesis & physical design tool. We evaluated our method for industrial designs with large circuits and long simulation times. When applied in the P&R stage, our methodology achieved a dynamic power reduction of 5.02% on average compared to the RTL-SAIF flow. In addition, by selectively introducing activity window profiling, runtime was reduced without significant total power change, preventing the design TAT increase of timing-based simulation. Finally, our new approach was introduced into real-world implementations without exception.

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