Presentation
Central DMA IP Verification Using Layered UVM Scoreboard
DescriptionWe present a scalable verification strategy for a highly concurrent, partitionable Central DMA (CDMA) IP that supports inter‑execution‑environment transfers, multicast distribution, and native PCIe integration/exposure. The verification challenge spans deep AXI ID usage, unbounded read‑data interleaving, QoS and route‑by‑port attributes, ECC/parity reactions, and heterogeneous bus interfaces (AXI/APB/ACE‑Lite), compounded by system scale (dozens of station interfaces, MSI‑X vectors, and configurable engines/rings). Our solution is a layered, channel‑aware UVM scoreboard that cleanly separates transfer‑intent binding from protocol and data checking. A transactor decodes descriptors to publish transfer intent; the scoreboard binds read IDs (via first read ADDR of source), captures source data, then binds write IDs (via first write address of destination) to perform beat‑accurate data comparisons. Completed transfers sends out to specialized scoreboards—AXI attribute/protocol/bandwidth, writeback, and MSI‑X coalescing/ordering—with a unified completion model. Results show >50% reduction in average debug time, faster coverage closure (especially DMA cross bins), simpler scenario extensibility through reusable checkers, and earlier detection of critical issues; to date, no silicon issues have been observed. This layered approach improves observability, triage clarity, and reuse, accelerating time‑to‑market while lifting verification quality for CDMA variants.
Event Type
Engineering Poster
TimeMonday, July 275:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor