Close

Presentation

Advanced Hard IP Integration Requirement Extraction and Checker
DescriptionMotivation: In SoCs 3rd party and TI internal hard IPs such as PHY, PLL, Dividers, etc are often required and integrated. An integration and specification document is often shared which contains the intricacies to be taken care during implementation. However, the integration requirements are often scattered across multiple pages, embedded on figures/tables, etc. The current manual approach of extracting, reviewing, and translating these requirements into actionable checklists is time-consuming and error-prone. The requirements can be scattered across different documents too. Eg ODP and efuse controller are expected to be in the same power domain but, the requirement is present in the fusefarm document and not in the ODP document. These need to be clubbed together and might be missed unless the user has read all documents.

Solution: An AI based automated approach in two phases. Phase 1 leverages AI-based document parsing to intelligently extract and categorize integration requirements into multiple categories - floorplan, IR, timing, placement etc. with automatically correlating cross-document dependencies. Phase 2 employs AI to translate these requirements into automated TCL-based checkers and where feasible, provide TCL based fix coding scripts.

Impact: The Physical Design (PD) team emerges as the most significant beneficiary of this AI-powered solution, as they are directly responsible for implementing majority of integration requirements extracted from specification documents. Experimental validation across various design integration documents have shown significant time saving up to 2 weeks and zero requirement omission rates, making it a scalable solution.

Future scope: While the current system requires prompt refinement and domain expertise for evolving IP types and documentation formats, future enhancements will incorporate automated prompt optimization to minimize specialist dependencies.