Presentation
Slack-Exploiting Load Splitting for IR-Drop Mitigation
DescriptionModern ICs face severe IR-drop challenges, leading to timing violations and reliability issues. Traditional mitigation methods like power grid reinforcement or global buffer sizing incur significant area/power overheads, while IRECO often degrades performance due to tight timing budgets. This paper introduces a novel "load splitting" methodology to address localized IR-drop. It strategically decomposes large fanout drivers into multiple smaller drivers, each handling a subset of loads. This approach effectively reduces current density in power grid segments, alleviating voltage drops without extensive power delivery network redesign or consuming valuable timing budget. Experimental results show load splitting significantly reduces IR-drop violations with minimal impact on timing. A TSMC N2 testcase demonstrated a 20% higher fixing rate compared to existing IRECO features, positioning this method as a practical and scalable solution for robust high-performance digital circuits in advanced technology nodes.
Event Type
Engineering Poster
TimeTuesday, July 285:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor