Presentation
Automotive Logic Test Power Management
DescriptionTest coverage, test time, and test power are tradeoff on automotive system logic test. Unlike test coverage and test time, power is critical factor which is hard to be predicted and evaluated when implementation. Logic test usually has large amount of registers toggled at the same time and results in scan shift IR drop which might fail the test. Reducing pattern toggle would result in longer test time. Time consuming iterations for months are required to validate and fine tune scan structure with lower peak current until IR analysis is completed
Automotive System Logic Test Power management includes two parts: Pseudo-CPM Analyzer for test current prediction, and ASKA + POWA for shift power reduction. It helps user to fine tune design during design phase and IR drops reduce 3.2% with add-on clock skew on real product. The product also met design spec on logic test's coverage/test time/power and got silicon proven.
Automotive System Logic Test Power management includes two parts: Pseudo-CPM Analyzer for test current prediction, and ASKA + POWA for shift power reduction. It helps user to fine tune design during design phase and IR drops reduce 3.2% with add-on clock skew on real product. The product also met design spec on logic test's coverage/test time/power and got silicon proven.
Event Type
Engineering Poster
TimeTuesday, July 285:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor
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