Presentation
Solving Memory Subsystem Verification Challenges for Multi-Instance Designs
DescriptionThis presentation specifies the DDR Memory controller verification for memory subsystem using hierarchical design aware Verification IP for recent generation of memory sub systems like DDR5, LPDDR5 etc. and how Cadence memory controller team has used a generic solution to describe such interconnect hierarchy in a modular and simple way. This approach defines a feature, associated construct to capture memory sub system and implementation of handshake mechanism with triggers (like commands) to enhance individual instance DRAM model to be able to get visibility into other DRAM devices present in the design that are sharing resources like data bus, ZQ registers etc. Presentation also given example of how this innovative solution has been used by Cadence memory controller IP and other external customers to enhance their sub system level verification to the next level while verifying protocol compliance for JEDEC define specification for multi-rank memory sub systems for DDR5 and LPDDR5 based designs. This solution can also potentially be applied to any Verification IP models to higher level protocol compliance checking.
Event Type
Engineering Poster
TimeMonday, July 275:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor
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