Presentation
Resistive Model-Based via Optimizatiion
DescriptionEMIR is a factor in chip performance and long-term reliability. Steps to address different causes of EMIR issues are taken across a number of tools in any design flow methodology. At the very last stage of the design cycle, via insertion by a EDA tool, such as Calibre DesignEnhancer is the last attempt to further optimize via arrangements in the physical chip design. The approach of via insertion by most software is an area-based computation. This paper discusses the benefits of a resistive model-based computation and suggests an implementation methodology. For proof-of-concept, the model used in this paper is fictional, but it illustrates the impact of resistance-based via selection on the ultimate aim of reducing EMIR in the face of increasing via choices of future technology.
Event Type
Engineering Poster
Engineering Presentation
TimeTuesday, July 285:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor