Presentation
The New Era of Digital Verification: a Revolution Driven by Agentic AI Acceleration
DescriptionDigital verification of integrated circuits faces critical challenges such as achieving extremely high functional and code coverage with full reliability, managing the complexity and significant time investment required by formal and UVM environments, and accelerating debugging processes to meet increasingly tight project schedules.
This paper presents a well-structured digital verification flow built around the ChipAgentsAI platform, illustrating a complete methodology that leverages agentic AI to correctly execute all key steps in the IC design verification lifecycle: from understanding the specification, to generating verification code and test plans, through to debugging and results analysis.
By drastically reducing manual effort and minimizing human errors, the solution improves both efficiency and verification quality and delivers unprecedented levels of automation, effectively addressing the growing complexity of modern IC designs.
In practice, the application of agentic AI tools enabled the discovery of previously unnoticed specification bugs, the generation of a larger number of assertions and covergroups, and the attainment of very high code and functional coverage metrics.
Notably, specification reading time was reduced by 15×, formal assertion generation by 240×, and UVM environment creation by 400×, significantly shortening the overall verification timeline.
These gains are achieved under the full control of the verification engineer: the tool executes only what it is explicitly asked to do and, starting from a clear and complete specification, the engineer guides the flow step by step and remains central in using ChipAgentsAI as a powerful ally to simplify, accelerate, and increase the accuracy of the verification process.
This paper presents a well-structured digital verification flow built around the ChipAgentsAI platform, illustrating a complete methodology that leverages agentic AI to correctly execute all key steps in the IC design verification lifecycle: from understanding the specification, to generating verification code and test plans, through to debugging and results analysis.
By drastically reducing manual effort and minimizing human errors, the solution improves both efficiency and verification quality and delivers unprecedented levels of automation, effectively addressing the growing complexity of modern IC designs.
In practice, the application of agentic AI tools enabled the discovery of previously unnoticed specification bugs, the generation of a larger number of assertions and covergroups, and the attainment of very high code and functional coverage metrics.
Notably, specification reading time was reduced by 15×, formal assertion generation by 240×, and UVM environment creation by 400×, significantly shortening the overall verification timeline.
These gains are achieved under the full control of the verification engineer: the tool executes only what it is explicitly asked to do and, starting from a clear and complete specification, the engineer guides the flow step by step and remains central in using ChipAgentsAI as a powerful ally to simplify, accelerate, and increase the accuracy of the verification process.
Event Type
Engineering Poster
TimeMonday, July 275:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor