Presentation
A Chip-Level DTCO Framework for Yield-Aware Back-End Design: Layout-Aware Misalignment Correction in DRAM
DescriptionWe propose a chip-level, layout-aware DTCO framework to correct deterministic interlayer misalignment. Using layout-driven features and machine learning, the proposed approach achieves ~70% variation reduction, enables fast inline prediction, and improves yield on silicon-proven products.
Event Type
Engineering Poster
TimeTuesday, July 285:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor