Presentation
UCIe-A 64GT/s High Speed Integrated Design and SI/PI Comparison of CoWoS-S/L/R
DescriptionFor AI/HPC application, ASIC development with heterogeneous integration of 2.5DIC through UCIe has been a critical demand in recent years. UCIe consortium proposes advanced packaging interface protocol of data width 64-bit with 64GT/s in revision 3.0 on Aug., 2025, which is also beneficial for huge data transmission requirement. However, such UCIe-A 64GT/s integration also brings strict SI/PI design challenges at interconnects and power distributed networks (PDNs).
In addition, various advanced packaging technologies of 2.5DIC were proposed in recent decades, e.g., TSMC CoWoS and Intel EMIB. To fulfill chiplets integration at these various advanced packaging technologies, the related signal/power integrity design has also played a significant role at high speed integration from pre-layout to post-layout.
This presentation discusses the critical design factors, performance merits, and EDA workflows, based on TSMC three critical interposer technologies, i.e., CoWoS-S/L/R, regarding UCIe-A x64E, 64GT/s integration, where the design using CoWoS-S can achieve good margins of eyewidth of 0.9UI and Vpp of 5.92mV. This work can provide an in-depth view and reference for successful integration of signal/power integrity aware design.
The content is organized as, (1) UCIe-A 64GT/s, x64E, design scope and EDA workflows; (2) signal integrity comparison; (3) power integrity comparison; (4) summary.
In addition, various advanced packaging technologies of 2.5DIC were proposed in recent decades, e.g., TSMC CoWoS and Intel EMIB. To fulfill chiplets integration at these various advanced packaging technologies, the related signal/power integrity design has also played a significant role at high speed integration from pre-layout to post-layout.
This presentation discusses the critical design factors, performance merits, and EDA workflows, based on TSMC three critical interposer technologies, i.e., CoWoS-S/L/R, regarding UCIe-A x64E, 64GT/s integration, where the design using CoWoS-S can achieve good margins of eyewidth of 0.9UI and Vpp of 5.92mV. This work can provide an in-depth view and reference for successful integration of signal/power integrity aware design.
The content is organized as, (1) UCIe-A 64GT/s, x64E, design scope and EDA workflows; (2) signal integrity comparison; (3) power integrity comparison; (4) summary.
Event Type
Engineering Poster
TimeMonday, July 275:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor