Presentation
Physics-Aware CNN-Based IR Drop Risk Prediction for Fast and Reliable SRAM Placement Optimization
DescriptionDynamic IR drop in advanced nodes poses a critical challenge for SRAM memory placement, where dense instance packing and synchronized switching currents frequently cause localized power integrity violations. Conventional IR Drop analysis relies on full-chip simulation after placement, making it impractical for early-stage placement optimization.
This work presents a CNN-based IR Drop-risk prediction framework tailored for SRAM macros, leveraging physics-aware features including local 3×3 peak current patterns, bump-to-instance power resistance, bump-to-instance ground resistance, bump distance, and instance aspect ratio. The proposed model classifies IR Drop-critical SRAM instances with high recall, enabling conservative detection of worst-case power integrity risks.
By integrating the learned IR Drop-risk model into a placement-aware cost formulation, our approach identifies vulnerable SRAM regions without exhaustive simulation and provides actionable guidance for placement refinement. Experimental results demonstrate that the proposed method effectively captures worst-case IR Drop behavior in SRAM-dominated designs, offering a scalable and analysis-efficient alternative to traditional IR signoff flows.
This enables IR Drop-aware SRAM placement decisions at a fraction of the cost of traditional signoff-driven optimization.
This work presents a CNN-based IR Drop-risk prediction framework tailored for SRAM macros, leveraging physics-aware features including local 3×3 peak current patterns, bump-to-instance power resistance, bump-to-instance ground resistance, bump distance, and instance aspect ratio. The proposed model classifies IR Drop-critical SRAM instances with high recall, enabling conservative detection of worst-case power integrity risks.
By integrating the learned IR Drop-risk model into a placement-aware cost formulation, our approach identifies vulnerable SRAM regions without exhaustive simulation and provides actionable guidance for placement refinement. Experimental results demonstrate that the proposed method effectively captures worst-case IR Drop behavior in SRAM-dominated designs, offering a scalable and analysis-efficient alternative to traditional IR signoff flows.
This enables IR Drop-aware SRAM placement decisions at a fraction of the cost of traditional signoff-driven optimization.
Event Type
Engineering Poster
TimeTuesday, July 285:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor