Presentation
A Novel Automated Methodology Python Driven for Test Coverage Improvement via Fault Injection and Simulation
DescriptionThe increasing complexity of digital circuits and stringent functional safety standards, such as ISO 26262 and IEC 61508, require test coverage levels above 99%, which often leads to significant area overhead due to traditional Design For Testability (DFT) techniques. This work presents a novel automated methodology, driven by a Python script, that combines ATPG patterns generated by TestMAX ATPG with functional fault simulation run using VC_Z01X to significantly improve test coverage without additional area overhead. The methodology was validated on a STMicroelectronics' synchronous step-down regulator, showing coverage improvements from 78.87% to 92.90% in full-scan configuration and from 42.09% to 84.25% in partial-scan mode, while drastically reducing ATPG untestable faults. The automated flow leverages the existing functional testbench, enhancing verification efficiency and repeatability. This approach advances the trade-off between achieving high test coverage and minimizing area impact, offering valuable benefits for safety-critical applications and designs with strict area constraints.
Event Type
Engineering Poster
TimeMonday, July 275:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor