Presentation
Overcoming Accuracy and Scalability Limits in Multi-Port On-Chip Electromagnetic Simulation Using a Hybrid Partial Elements Equivalent Circuit Solver
DescriptionTraditional design cycles include multiple tapeout and measurement cycles to achieve optimal performance. This increase in cost and delayed product introduction is no longer attractive with expensive advanced process nodes and working with condensed design cycles. Electromagnetic (Emag) simulation must play a role in reducing design time and cost. There are many challenges with on-die Emag extraction: difficult port assignment because of poorly defined return paths, high port counts, high computational cost (i.e., long simulation times and RAM used) because of the mesh density required with full-wave solvers to accurately model skin and proximity effects for the high aspect ratio geometry found on die, and long SPICE run times when using the S-parameter outputs of Emag simulations.
We propose a partial element equivalent circuit method with random walk to extract the layout and generate rational function models (RFMs) to address speed and capacity concerns at all stages of analysis. We prove efficacy by running Emag extractions for 3.55 to 7.99 GHz voltage-controlled oscillator (VCO) inductor and capacitor resonant tank circuits and using S-parameter and RFM outputs with SPICE simulations to show ~1.4X reduction in SPICE simulation time using RFMs and prove accuracy by matching measured results within 6%.
We propose a partial element equivalent circuit method with random walk to extract the layout and generate rational function models (RFMs) to address speed and capacity concerns at all stages of analysis. We prove efficacy by running Emag extractions for 3.55 to 7.99 GHz voltage-controlled oscillator (VCO) inductor and capacitor resonant tank circuits and using S-parameter and RFM outputs with SPICE simulations to show ~1.4X reduction in SPICE simulation time using RFMs and prove accuracy by matching measured results within 6%.
Event Type
Engineering Poster
TimeTuesday, July 285:00pm - 6:00pm PDT
LocationDAC Pavilion, Exhibit Floor